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##################################################### # DESIGN OBJECTIVES DOCUMENT FOR ANALOG VHDL 1076.1 # ##################################################### DOCUMENT HISTORY ================ 0.1 2-apr-92 Hazem El-Tahawy Initial version prepared by Berge, El Tahawy, Rodriguez and Rouqier 0.2 11-may-92 Robert Cottrell Revised following meeting at European VHDL Forum in Santander, Spain, 28-apr-92 +++++++++++++++++++++++++++++++++++++ Memo on the analog extensions to VHDL +++++++++++++++++++++++++++++++++++++ -0- Introduction ================ This memo, prepared by J.M.BERGE, H.El TAHAWY, D.RODRIGUEZ and D. ROUQUIER, presents the main ideas contained in the requirements concerning the analog extensions to VHDL. It contains as few syntactic examples as possible. The extended VHDL is called VHDL-A. Some ideas are explicitly supported by one or several requirements; the corresponding requirement numbers are then listed (between brackets) after the corresponding paragraph. Other ideas are not explicitly supported by any requirement, but appeared during analysis, or during discussions. -1- List of relevant requirements ================================= The numbering below was indicated in a list of requirements prepared by W.NEBEL in March 1991. A01 Mark BROWN Continuous time A02 Mark BROWN Conversion between Continuous and Discrete time A03 Mark BROWN Network of interconnected elements A04 Mark BROWN Port behavior A05 Mark BROWN Operators A06 Mark BROWN Error tolerance A07 Mark BROWN Miscellaneous requirements A17 A.S.GILMAN Analog Modeling A18 A.S.GILMAN Physical quantities A19 A.S.GILMAN Baseline Character set E12 C. LE FAOU et al New key-words and electrical objects E13 C. LE FAOU et al Input parameter for entities E14 C. LE FAOU et al Package and user library for electrical modeling E16 D.ROUQUIER New key-words and underlying semantics for electrical modeling E46 M.ALTMAE Correspondence between VHDL objects and alternative representations in other netlist formats E47 M.ALTMAE Modify the VHDL initialization to include DC analysis for analog parts E48 M.ALTMAE Specified interface semantics between digital and analog parts of a design E62 D.RODRIGUEZ et al Dimensional equations E63 D.BORRIONNE et al New key-words and electrical objects modification and review of CLF+1 (= E12) E64 D.BORRIONNE et al Access to the current value crossing an electrical component The numbering below concerns "new" analog requirements gathered by M.ALTMAE; it is provisional, especially concerning requirements from the North-American chapter ... E65 D.ROUQUIER et al At least two labels E66 D.ROUQUIER et al Re-use digital constructs E67 D.ROUQUIER et al Definition of analog time E68 D.ROUQUIER et al Time synchronization E69 D.ROUQUIER Portability of analog models E70 D.ROUQUIER Use of existing methods E71 D.ROUQUIER et al User control over digital to analog interactions E72 D.ROUQUIER et al User control over analog to digital interactions E73 N.WHITAKER Dimensional analysis of physical types E74 D.ROUQUIER Domain of application E75 D.ROUQUIER Several modeling techniques E76 T.RAHKONEN consistency checks for excitations and results in different analogue simulators E77 A.PATTERSON Analogue modelling requirements in VHDL E78 D.ROUQUIER Mixed entities required E79 D.ROUQUIER Implementation issues A176 C.USSERY Single Timing Semantics A177 C.USSERY Pass-through of analog values A178 C.USSERY Fully intermixed designs A179 K.NOLAN Specification of initial analog conditions A180 K.NOLAN Specification of non-conserved analog systems -2- General Guidelines ====================== The following sections provide general guidelines for the design of VHDL-A: -2-1- Scope of the language ========================= VHDL-A should be suitable for the description and simulation of mixed, analog- digital, systems. No synthesis semantics is taken into account. -2-2- Digital aspects =================== VHDL-A will be a "super-set" of VHDL-92; any description that is valid in VHDL- 92 will also be valid in VHDL-A, WITH THE SAME SIMULATION RESULTS. ==--> ( A17 ) The only permitted exception to this is that new keywords introduced into the language may conflict with identifiers used in a VHDL-92 description. -2-3- Analog aspects ================== The analog part of VHDL-A should be targeted primarily towards the following applications: - DC and transient analyses - electronic circuits (OpAmps, PLLs, comparators, ...) - lumped-element systems ==--> ( E74 ) Attention should be paid to ensure that frequency analysis is possible (for purely analog descriptions), provided that this does not have too great an impact on the language. ==--> ( A3 ; A5 ) Also mixed, time-frequency analysis (MFTA) could be considered. ==--> ( A17 ) The other domains (mechanical, thermal, ...) could be easily introduced as they are analogous to the electrical domain. The micro-wave domain will not be taken into account. ==--> (this is contradiction with part of requirement #A17) Contacts should be taken with MHDL. The semantics of analog simulations will obviously be different from that of digital simulations; the syntax of analog descriptions should also be specific (to clearly identify the analog parts). Analog descriptions ought to re-use existing (VHDL-92) syntax where appropriate, for such constructs as expressions, function calls, if-then-else statements, ... ==--> ( E66 ) -2-4- Mixed aspects ================= A few, basic, mechanisms will be provided to allow analog parts and digital parts of a mixed circuit to interact. ==--> ( A2 ; A3 ; A5 ) The places where such interactions occur will be explicitly described by the user. ==--> ( E71 ; E72 ) The basic A/D,D/A interaction mechanisms of VHDL-A will be completely defined, and will make no use of the "foreign interface" of VHDL-92 (this not in contradiction with paragraph -3-). In other words, analog will not be "foreign" to VHDL-A. Together with the time synchronisation issues (see below, paragraph -16-), the guidelines contained in this paragraph should ensure a reasonable degree of portability, while giving enough freedom to the implementation. The intention is to maintain portability without defining the simulation algorithm. Further study is required on the meaning of portability. Further study id required on the restrictions which may be required on the conbination of analog and digital constructs. (but note ==--> A178) -3- Analog structures ===================== Using VHDL-A, it should be possible to describe the structural composition of analog sub-circuits connected by analog wires. ==--> ( A3 ; E12 ; E14 ; E63 ) -3-1- Similarities ------------------ For this purpose a number of aspects are very similar to the corresponding ones in the digital domain, namely : - blocks - components - configuration of a component onto an "entity-architecture pair" - generics - generate statements ==--> ( A3 ; E14 ) For these aspects , it should be possible to re-use the existing syntax. ==--> ( E66 ) -3-2- Differences ----------------- On the other hand, some aspects are very specific to analog, namely : - the analog ports (provisional name : PINs) of an analog component are characterized by a voltage accross the PIN and a current flowing through the PIN. ==--> ( A4 ; E12 ) - the interactions between an analog component and its environment are always "two-way" (not "in" or "out" ; the "inout" digital mode does not seem appropriate either). The terme "binding" has been used. ==--> ( A3 ; E63 ) - the analog wires (provisional name : NODEs) of an analog structure are characterized by a voltage. ==--> ( E12 ) - the connection of several PINs to a NODE means that : + all PINs must have the same voltage + the sum of PINs currents must be zero (Kirchoff's current law, or KCL). ==--> ( A1 ; A4 ; E12 ; E63 ; E77 ) (the two above assumptions might not hold in micro-wave circuits ...) - analog components may also need "parameters" ; parameters may be defined as generics whose value may vary during simulation. ==--> ( E13 ) For these aspects, new syntax has to be created. ==--> ( E66 ) It will be necessary to specify a clear convention concerning the direction of currents (entering or leaving the components). By changing the definition of the "accross" and "through" quantities, and by keeping KCL and KVL (equal "accross" quantity on a "node", null sum of "through" quantities on a node), other domains (mechanical, thermal, ...) can easily be introduced. -4- Analog behaviors ==================== To describe the behavior of an analog part in a behavioral (not structural) way, two styles should be provided : -4-1- Relations --------------- The behavior of an analog part may be described by an un-ordered set of differential equations. ==--> ( A4 ; E12 ; E14 ; E70 ; E75 ; E79 ) note : - Each of these equation is added to the set of equations to be solved to perform analog simulation - Other equations come from the structural description - adding an equation to the equation set should be complemented by adding an independent variable to the set of variables. -4-2- Procedural models ----------------------- The behavior of an analog part may be described by a procedure, returning branch currents as a function of node voltages. Each of these procedures is called, by the simulator during analog simulation, to find node voltages satisfying KCL. ==--> ( A4 ; E70 ; E75 ; E79 ) NOTE : - it might be usefull to allow a procedural model to return also voltages as functions of currents (e.g. for an inductance). Remark : - These two styles ("relations" and "procedural models") will form the "core" of the analog part of VHDL-A, and should be designed with great care. - It might be interesting to allow mixing both styles within the same analog part, like in FAS or MAST. -4-3- Access to voltages and currents ------------------------------------- For analog behavioral modeling (and for A-to-D interactions), it is necessary to designate the voltage or the current of a PIN (seen from within a component). ==--> ( E14 ) It is also useful to designate a branch current or a node voltage (seen from outside components). ==--> ( E64 ) The following notations have been proposed : PIN1.V : access to the voltage of a pin PIN1.I : access to a pin current NODE1.V : access to the voltage of a node COMP1.PIN2.I : access to a branch current The above notations are provisional and purely syntactic, and do not mean that a PIN or NODE is represented by a "record" (the exact representation is left to the implementation). They may be used to allow reading, or writing, or within an equation. -5- Analog-to-Digital interactions ================================== The user must be given control over the exact transformations used in the A-to-D interactions ==--> ( E48 ; E72 ) A user-supplied thresholding function is required to ensure that digital events are triggered only when "significant" changes occur in the analog part. ==--> ( A5 ; E72 ) The basic mechanisms could be restricted to : - a digital process may read an analog value (voltage or current) ; - a digital process may be made "sensitive" to an analog value (and in this case the thresholding function is used to decide when to trigger the process ; this is similar to the "monitor" construct proposed by M.BROWN and B.HANNA, but more general). ==--> ( E72 ) Following this (and paragraph -5-), it should not be legal to connect a PIN to a signal. ==--> ( E79 ) -6- Digital-to-Analog interactions ================================== The user must be given control over the exact transformations used in the D-to-A interactions ==--> ( E48 ; E71 ) The basic mechanism(s) could be restricted to : - an analog behavioral part (see paragraph -7-) may read a digital signal. ==--> ( E71 ) In this case a user-supplied "slope function" might be required, to avoid numerical problems due to discontinuities in the analog part. This "slope function" is similar to the "waveform generator" proposed in A5, but less general. Following this (and paragraph -5-), it should not be allowed to connect a PORT to a node. ==--> ( E79 ) -7- Entities ============= Entities in VHDL-A may have PINs and PARAMETERs in addition to PORTS and GENERICs ; following this line, entities may be digital, analog, or mixed. ==--> ( E78 ; A177 ) -8- Architectures ================== Architectures in VHDL-A may contain NODEs and "Analog-Black-Boxes" (see paragraph -7-) in addition to SIGNALs and PROCESSes ; following this line, architectures may be digital, analog, or mixed. ==--> ( A177 ; A78 ) In addition to GENERIC MAP and PORT MAP, components will have "PIN MAP" and "PARAMETER MAP" ; same for blocks. ==--> ( E63 ) Analog-to-digital and digital-to-analog interactions will occur only within architectures containing PROCESSes and "Analog-Black-Boxes", and making use of one of the basic mechanisms described in paragraph -8- or -9-. ==--> ( E79 ) -9- Time derivative ==================== Time derivative is necessary for analog behavioral modeling. ==--> ( A5 ; E12 ; E70 ; E77 ) It must be possible to apply it to any analog quantity : - node voltage - branch current - pin voltage - pin current - user-defined extra independant variable (whether within a "relation" or within a "procedural model") Also integral might be usefull (at least "from 0 to now"). -10- Math package ================= For analog behavioral modeling a specific mathematical package is required, providing useful functions such as sine, cosine, exp, log, ln, complex numbers and associated operations, ... ==--> ( A7 ; E77 ) Also "PWL" functions could be found in this package. -11- Time, time synchronisation, initialisation =============================================== The initialisation of a mixed model must include DC analysis for the analog parts (in addition to the normal procedure for the digital parts) ; this may involve iterations. ==--> ( E47 ; A179 ) The simulation of a mixed model requires that events on digital signals and evolutions of analog quantities be ordered along a single time axis. ==--> ( A2 ; E67 ; E68 ; A176 ) The definition of time synchronisation between analog and digital parts should be complete and precise enough to ensure a reasonable degree of portability. ==--> ( E68 ; E69 ) and it should be transparent to the user (no explicit use of "last active postponed process"). -12- Physical Units =================== The language should support dimensional analysis. ==--> ( A18 ; E62 ; E73 ; E77 ) (to be defined carefully !). -13- Detailed analysis of available requirements ================================================ A01 Mark BROWN Continuous time --------------------------------------- idea #1 : continuous time supported (analog quantities vary continuously in time but the simulator computes them only at discrete time-points) idea#2 : analog simulation algorithms are proprietary supported (the analog part of the VHDL-A LRM will be less detailed than the digital part) idea #3 : Kirchoff's laws form the basis of the semantics for analog simulation supported A02 Mark BROWN Conversion between Continuous and Discrete time ----------------------------------------------------------------------- supported A03 Mark BROWN Network of interconnected elements ---------------------------------------------------------- no direction : supported a node connects two or more terminals : supported VHDL-92 component statements are good for analog structures : supported N-Port theory : not understood (please provide tutorial !!) a branch between two terminals : branch current not unique !? modal and domain conversions : ?? A04 Mark BROWN Port behavior ------------------------------------- KCL and KVL : supported branch current seen as function of other analog quantities : supported modeling by relationship : supported (assuming "relationship" is the same as "equations") A05 Mark BROWN Operators --------------------------------- threshold function for A-to-D : supported waveform operator for D-to-A : supported (to be refined) time derivative : supported transformation between time and frequency, partial derivative : ?? A06 Mark BROWN Error tolerance --------------------------------------- not understood A07 Mark BROWN Miscellaneous requirements -------------------------------------------------- math package for transcendental operations (and floating-point exponent) : supported complex numbers (rectangular or polar) : supported (but it is second-priority for transient analysis of mixed circuits) physical units : to be clarified A17 A.S.GILMAN Analog Modeling --------------------------------------- not completely understood not supported : micro-wave circuits ; use of "concurrent" (global ?) variables to model analog parts ; supported : the analog part operates in parallel with the digital one ; simulation algorithm is implementation-defined ; upward-compatiblity ; for time derivative, 'DOT is an interesting alternative to d-dt( ) ... A18 A.S.GILMAN Physical quantities ------------------------------------------- not completely understood supported : dimensional analysis in the language ; floating-point values for physical quantities A19 A.S.GILMAN Baseline Character set ---------------------------------------------- not considered (already considered by VHDL-92) E12 C. LE FAOU et al New key-words and electrical objects ------------------------------------------------------------ idea #1 : modeling by equation supported (note : adding an equation to the equation set should be complemented by adding an independent variable to the set of variables ...) idea #2 : essentially a re-phrasing of Kirchoff's laws supported idea #3 : syntactic issues ("type electrical is record .....) it is perhaps too early to propose detailed syntactic forms idea #4 : time derivative supported E13 C. LE FAOU et al Input parameter for entites --------------------------------------------------- supported (except using parameters in the digital domain ; this needs further study) E14 C. LE FAOU et al Package and user library for electrical modeling ------------------------------------------------------------------------ It is too early to propose detailed syntax ; the examples are all very simple ones, and tend to suggest that this method is limited to elements having only two pins, possibly parameters, and no internal states. To be studied further. E16 D.ROUQUIER New key-words and underlying semantics for electrical ----------------------------------------------------------------------------- modeling not considered (too long, too syntactical ; the main ideas have been rephrased in subsequent requirements by the same author). E46 M.ALTMAE Correspondence between VHDL objects and alternative --------------------------------------------------------------------------- representations in other netlist formats not completely understood ; idea #1 : seems to suggest A-to-D and D-to-A interactions by direct connection of (vhdl) signals to (spice) nodes ; this seems the only way during the interim phase (using the "foreign interface" before VHDL-A is standardised) but it will not be the case in VHDL-A idea #2 : programs to adapt SPICE libraries to VHDL-A : supported E47 M.ALTMAE Modify the VHDL initialisation to include DC analysis ----------------------------------------------------------------------------- for analog parts supported (but we should find a way of avoiding iterations ...) E48 M.ALTMAE Specified interface semantics between digital and analog -------------------------------------------------------------------------------- parts of a design supported E62 D.RODRIGUEZ et al Dimensional equations --------------------------------------------- dimensional analysis in the language : supported detailed syntax to do so : too early E63 D.BORRIONNE et al New key-words and electrical objects modification and ----------------------------------------------------------------------------- review of CLF+1 (= E12) idea #1 : connecting several "PINs" to a "NODE" does not imply the same semantics as connecting several ports to a signal. supported idea #1 : proposed syntax too early E64 D.BORRIONNE et al Access to the current value crossing an electrical -------------------------------------------------------------------------- component need to access branch currents : supported detailed syntax for that purpose : too early E65 D.ROUQUIER et al At least two labels ------------------------------------------- not considered (not technical ; in fact, as there will be two different standards, it will be easy to check whether a given simulator is conformant to 1076 or to 1076.1). the criterion to tell whether a circuit is digital, analog, or mixed will be known only after elaboration. E66 D.ROUQUIER et al Re-use digital constructs ------------------------------------------------- supported (in fact, to be monitored during the detailed design of the language) E67 D.ROUQUIER et al Definition of analog time ------------------------------------------------- supported E68 D.ROUQUIER et al Time synchronisation -------------------------------------------- idea #1 : conversion between analog time and digital time : supported idea #2 : achieve unique time axis : supported idea #3 : proposed strategy : to be studied in greater details ; such a model (of the mixed simulator) must be viewed as conceptual, otherwise we might enter domain of "over-specification". E69 D.ROUQUIER Portability of analog models ---------------------------------------------------- to be analysed by vendors of mixed simulators ! E70 D.ROUQUIER Use of existing methods ----------------------------------------------- general : supported modified nodal method : over-specification ? procedural models : supported (to be refined) extra equations (and associated extra variable) : supported old value, time-step : see procedural models time derivative : supported E71 D.ROUQUIER et al User control over digital to analog interactions ------------------------------------------------------------------------ general : supported details depend on the exact definition of analog behavioral modelling in VHDL-A. the problem of discontinuity may be solved by the "slope function" associated with any signal used (in read-only mode) in the analog part. E72 D.ROUQUIER et al User control over analog to digital interactions ------------------------------------------------------------------------ supported E73 N.WHITAKER Dimensional analysis of physical types -------------------------------------------------------------- supported E74 D.ROUQUIER Domain of application --------------------------------------------- supported E75 D.ROUQUIER Several modeling techniques --------------------------------------------------- supported (the syntax of "analog procedural models" may be similar to that of digital processes, but the semantics will be completely different) E76 T.RAHKONEN consistency checks for excitations and results in ------------------------------------------------------------------------- different analogue simulators not understood This text seems to refer to a situation where different simulators are used in a very loosely coupled way, and the simulation of the whole circuit requires a lot a manual (and error-prone) operations, to feed the results of one simulator as stimuli to another simulator. It does not seem to envisage true mixed-mode simulation in VHDL-A. E77 A.PATTERSON Analogue modelling requirements in VHDL --------------------------------------------------------------- supported (perhaps phase-angle descriptions are second priority). E78 D.ROUQUIER Mixed entities required ----------------------------------------------- supported E79 D.ROUQUIER Implementation issues --------------------------------------------- supported A176 C.USSERY Single Timing Semantics ----------------------------------------------- idea #1 : extensions to the timing model (due to analog) should be incorporated within VHDL-92 : nice idea, but it is too late now idea #2 : achieve a single simulation cycle mechanism : supported A177 C.USSERY Pass-through of analog values ----------------------------------------------------- supported assuming that the mixed component in the associated example will have a mixed interface (at least two PINs, possibly some ports) and will contain, in addition to its ("purely digital") behavior, a "connect statement" (still to be invented) to indicate that the two nodes (coming from the source and going to the reader) are connected. A178 C.USSERY Fully intermixed designs ------------------------------------------------ supported ("runtime statements" : to be clarified) ; closely linked to A177. A179 K.NOLAN Specification of initial analog conditions ------------------------------------------------------------------ supported also user-supplied "hints" before DC are usefull (to help DC converge faster) A180 K.NOLAN Specification of non-conserved analog systems --------------------------------------------------------------------- not understood ; please provide tutorial ! -14- Open questions =================== -14-1- Relations ---------------- This style of description has been illustrated in requirements E12 and E14, but only on simple examples (elements with only two pins, or structural equivalent circuit for the bipolar transistor). It is necessary to explore the limits of this style : - is it possible to describe an element having three or more pins using only equations ? - what if several relations are declared within one architecture (does this describe a "structure" ; will the relations interact through nodes) ? - use of "if-then-else" within relations ? - is it necessary to explicitely declare a new variable with each new equation ? -14-2- Procedural models ------------------------ This style of description has been described, with very few details, in requirements A4, E70 and E75. It is used in several existing simulators (FAS, MAST, also M). It is very natural if the equation-set is built using the "modified nodal method" (each node corresponds to one variable : the node voltage, and one equation : KCL). It may include such features as access to the 'old' value of an analog quantity, access to the value of the time-step, ... It is necessary to explore also the limits of this style. -14-3- Modifications to the digital "kernel" -------------------------------------------- It will be necessary to introduce at least some modifications to the digital part of VHDL-92 to allow for well-defined mixed-mode descriptions and simulations. These modifications will emerge from the A-to-D interaction mechanisms, and from the problem of time synchronisation. The following could be sufficient : -1- the wait statement is extended to allow processes to be sensitive to analog quantities ; examples : wait on N.V ; wait on PIN1.I ; wait on COMP1.PIN2.V ; (note-1 : the visibility rules will have to be refined) (note-2 : a thresholding function is required, associated with the analog quantity to which a process is sensitive) this sensitivity takes effect as explained below. -2- the simulation cycle is modified : -2-1- when the digital "kernel" reaches the point where all processes have been run and have suspended (including "postponed" processes), instead of advancing time (to the "next digital date", which is strictly greater than the current date), the the digital kernel should be capable of halting and giving control back to some "general kernel", which will take care of analog simulation. -2-2- the digital kernel is capable of being re-started by the "general kernel" with the following order : advance time to the "next digital date" and perform normally at that date (in this case there is no real modification of the simulation cycle) ; -2-3- the digital kernel is also capable of being re-started by the "general kernel" with the following order : advance time to date To (with To strictly smaller than the "next digital date") and at that time, accept "unforeseen events". These events come from the analog part, and as far as the digital kernel is concerned, they simply imply resuming the execution of one or several processes currently suspended on a "wait on N.V" statement. with these modifications, and with a few assumptions on the analog simulator, time synchronisation can be acheived. -14-4- Assumptions on the analog simulator ------------------------------------------ When started, the analog simulator never produces "zero-delay-events" (in other words, its time-step is never zero) ; this seems a reasonnable assumption to place on any analog simulator, and it might be crucial when specifying time synchronization. The analog simulator can not tell its "next analog date" (date of the next time- step to be computed by the analog simulator). On the other hand, when computing a time-step, it can store old values (values of the previous time step) ; thus it can be told either to "accept" a time-step (forget old values) or to "reject" a time-step and to compute (possibly by interpolation) a shorter one. This is a soft form of backtracking. with these assumptions, and with the above modifications on the digital simulator, time synchronisation can be acheived. -14-5- Miscellaneous questions ------------------------------ Limits of the LRM : Will the LRM describe the structure of the mixed simulator, the time synchronization mechanism, the method for building the equation-set, the method for solving it ? Error tolerance ( A06 ) and portability ( E69 ) ; N.I returns 0 or epsilon ? 64 bits ? (left to the implementation ?) statement for "connecting" two nodes ( A177 ) ? "node-set" to help DC